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Designing with Xilinx® FPGAs: Using VivadoFrom Springer
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This book helps readers to implement their designs on Xilinx� FPGAs. The authors demonstrate how to get the greatest impact from using the Vivado� Design Suite, which delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. This book is a hands-on guide for both users who are new to FPGA designs, as well as those currently using the legacy Xilinx tool set (ISE) but are now moving to Vivado. Throughout the presentation, the authors focus on key concepts, major mechanisms for design entry, and methods to realize the most efficient implementation of the target design, with the least number of iterations.
- Sales Rank: #331616 in Books
- Published on: 2016-10-21
- Original language: English
- Number of items: 1
- Dimensions: 9.21" h x .63" w x 6.14" l, .0 pounds
- Binding: Hardcover
- 260 pages
From the Back Cover
This book helps readers to implement their designs on Xilinx� FPGAs. The authors demonstrate how to get the greatest impact from using the Vivado� Design Suite, which delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. This book is a hands-on guide for both users who are new to FPGA designs, as well as those currently using the legacy Xilinx tool set (ISE) but are now moving to Vivado. Throughout the presentation, the authors focus on key concepts, major mechanisms for design entry, and methods to realize the most efficient implementation of the target design, with the least number of iterations.
About the Author
Sanjay Churiwala is Senior Director of Engineering for Xilinx India Technology Services. He has extensive experience in the field of EDA and semiconductors R&D, as well as customer-interaction. He specializes in Clock Domain Crossings and Synchronization,�STA, Power, Synthesis, Simulation, Rule based static checkers, Cell Characterization and Modeling.
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